OV2640 Frequency Calculator

Notes:

• Clock formulas (OV2640 has no PLL - only the CLKRC doubler/divider and the DSP DVP prescaler; see ov2640.c set_window and OV2640_DS.pdf):

  CLK       = XVCLK * (clk_2x ? 2 : 1) / (clk_div + 1);   // CLKRC 0x11 (sensor bank)
  PIXRATE   = CLK / (CIF mode ? 2 : 1);                   // sensor pixel rate (1/tP)
  FPS       = PIXRATE / (tLINE * frame_lines);
  PCLK      = pclk_auto ? (DSP controlled) : CLK / pclk_div;  // R_DVP_SP 0xD3 (DSP bank)
  

• Sensor mode timings are fixed (datasheet Figures 13-15): UXGA tLINE=1922 tP × 1248 lines, SVGA tLINE=1190 tP × 672 lines, CIF tLINE=595 tP × 336 lines. Changing the DSP window or output size does not change the frame rate - only COM7 mode and CLKRC do.
• CIF mode ÷2 is empirical: the datasheet does not state it, but measured FPS in this project (QVGA/CIF 60 FPS at XVCLK 12 MHz, doubler ON) matches pixel rate = CLK/2 in CIF mode. UXGA/SVGA modes match pixel rate = CLK exactly (SVGA 30 FPS, UXGA 10 FPS at 12 MHz).
• JPEG modes in this project always use clk_2x=1, clk_div=0, pclk_manual, pclk_div=8 (CIF/SVGA modes) or 12 (UXGA mode). Non-JPEG (YUV) path uses pclk_auto and clk_div=7 (3 in CIF mode) instead.
• OV2640 "high FPS" mode is implemented by raising XCLK from 12 to 16 MHz (main.cpp), and only for VGA 640x480, VGA16 (640x360) and SVGA16 (800x456): 30 → 40 FPS.
• On OV2640, VGA16 and SVGA16 share the same SVGA-mode 16:9 window (offset_y=72, window 800x456) via set_res_raw. SVGA16 outputs it unscaled (800x456); VGA16 engages the DSP scaler (ZMOW/ZMOH) to output a true 640x360 — FPS is identical since frame rate depends only on the sensor mode raster. 1024x576 uses a UXGA-mode 16:9 window (offset_y=150, window 1600x900).
• UXGA-mode FPS bookkeeping: theoretical FPS is 10.0 at XVCLK 12 MHz; the vmodes table lists 12 FPS nominal for XGA/XGA16/SXGA/HD, and main.cpp comments mention ~13 FPS measured for the 16:9 sub-window modes.
• OV2640 is not supported on ESP32-C5 in this project - the platform list has no C5 entry. XVCLK datasheet range: 6-24 MHz (16 MHz high-FPS mode is in range; nominal is 24 MHz where sysclk becomes the "48" in the R_DVP_SP formula).
• R_DVP_SP formula per datasheet: DVP PCLK = sysclk/[6:0] (YUV/JPEG), sysclk/(2×[6:0]) (RAW), where sysclk is CLK after the CLKRC doubler/divider (nominally 48 MHz at XVCLK 24 MHz, doubler ON).
• All frequencies in Hz