OV3660 Frequency Calculator

Notes:

• Clock formulas (from ov3660.c calc_sysclk, PLLS registers 0x303A-0x303D):

  REFIN   = XVCLK / pll_pre_div;                    // /1, /1.5, /2, /3      (0x303D[5:4])
  VCO     = REFIN * pll_multiplier * pll_root_2x;   // multiplier 1..31      (0x303B)
  PLLCLK  = pll_bypass ? XVCLK : (VCO * 2 / pll_sys_div / seld5_2x);  // seld5: /1, /2, /2.5
  SYSCLK  = PLLCLK / 4;
  PCLK    = PLLCLK / 2 / (pclk_manual ? pclk_div : 1);
  

• FPS formula: FPS = SYSCLK / (HTS × VTS). Binned modes normally use VTS = total_y/2 + 1; ESP32 VGA/SVGA deliberately override VTS to 783.
• VCO range is not published for the OV3660 PLLS; stock configs run 160-200 MHz, project presets up to ~293 MHz. Values above 400 MHz are flagged.
• Classic ESP32 has no OV3660 high-FPS mode because the experimental timing corrupts frames; S3/C5 support high-FPS binned modes.
• 1024x576 and 1280x720 share one dedicated 16:9 timing: HTS=1920, VTS=1040, active source 1728x972, no binning. 1280x720 previously used a wider window (HTS=2172, VTS=1128, active source 1920x1080) for a slightly larger FOV, but that window gives the image a cyan/red cast on OV3660 - measured on ESP32-C5, the cast is unaffected by pixel clock and vertical blanking and disappears only on this window.
• ESP32 (esp32cam) quirks: VGA/SVGA use a centered 1920x1440 source, HTS=2172, VTS=783 and a 51.67 MHz SYSCLK for 30.38 FPS. The stock full-array 2048x1536 source produces unstable VSYNC cadence. Other modes follow the same binning, special-mode and PLL branches as ov3660.c.
• All frequencies in Hz