OV5640 Frequency Calculator

Capture platform:

XVCLK Frequency (Hz):

pll_pre_div (1,2,3,4,6,8):

pll_multiplier (PLL: 4-252):

root_2x_div (0x3037[4]):

pll_bypass (0x3039[7]):

pll_sys_div (1-15):

bit_div_2x (0x3034[3:0]):

pll_pclk_root_div (0=1x, 1=2x, 2=4x, 3=8x):

pclk_manual:

pclk_div (1-31, ignored in auto):

FPS:

Notes:

Clock formulas:

REFIN   = xclk / pll_pre_div;
VCO     = REFIN * pll_multiplier;
PLL_CLK = pll_bypass ? xclk : (VCO / pll_sys_div / root_2x_div * 2 / bit_div_2x);
SYSCLK  = PLL_CLK / 4;   // SCLK root divider fixed to /4 (driver writes 0x3108[1:0] = 2)
PCLK    = PLL_CLK / pclk_root_div / (pclk_manual ? pclk_div : 2);

FPS formula: FPS = SYSCLK / (HTS × VTS). The sensor row scan is driven by SYSCLK (ISP clock), not by PCLK. HTS=0x380C/0x380D, VTS=0x380E/0x380F.
Binning: when binning is active the driver programs VTS = total_y/2 and HTS = total_x−200 (width > 920) or 2060 (width ≤ 920); the Timing row, FPS and register output reflect this.
PCLK auto divider: the ÷2 used in auto mode (0x460C[1]=0) is an assumption inherited from the driver; the datasheet does not document the auto value.
All frequencies in Hz

OV5640 Frequency Calculator

Frequency Chain

Notes:

PLL Setup

Register Settings

Timing